Semiconductor Technology from A to Z

Everything about semiconductors and wafer fabrication

1. From Wafer to Individual Chip

After the wafer test, the wafer still exists as a single, continuous disc containing hundreds to several thousand individual dies, separated by narrow, unpopulated strips – the so-called scribe lines or dicing lanes. These strips contain no functional circuit structures and are deliberately reserved for the subsequent separation step.

During dicing (also called wafer sawing or die separation), the wafer is cut into individual dies along these scribe lines. This step marks the transition from the front-end of manufacturing, where all dies were still processed together on the wafer, to the back-end, where each die is handled individually from this point onward.

Before the actual separation, the wafer is typically mounted onto a thin, elastic carrier film (dicing tape) stretched over a metal frame. This film keeps the individual dies in their original position after sawing, preserving the spatial correspondence to the previously generated yield map.

2. Sawing Methods

The most widely used method is mechanical sawing with a thin, diamond-embedded circular blade (blade dicing). The blade rotates at very high speed (typically 20,000 to 60,000 revolutions per minute) and is continuously cooled and flushed with deionized water during cutting to dissipate frictional heat and remove sawing debris from the cut.

The width of the scribe lines limits how narrow the saw blade can be and how precisely the cut must be guided. As available scribe line width continues to shrink with ongoing miniaturization, alternative separation methods are gaining increasing importance:

  • Laser dicing: a focused laser beam separates the wafer either by direct ablation of material or by deliberately introducing internal micro-cracks (stealth dicing), along which the wafer is subsequently broken apart mechanically
  • Plasma dicing: the wafer is completely etched through along the scribe lines using an anisotropic dry etch process; this method produces particularly smooth, damage-free edges and is well suited for very thin wafers

Each method has specific advantages and disadvantages regarding cutting speed, mechanical stress on the material, and achievable edge quality, which is why the choice of separation method depends on the specific product and wafer layer stack.

3. Challenges and Quality Assurance

During mechanical sawing, fine chipping can occur at the edge of the cut – small fractures of the brittle silicon material. These micro-cracks can propagate further under mechanical or thermal stress during the component later operation, potentially compromising reliability. Sawing parameters – particularly feed speed, rotational speed and cooling – must therefore be carefully matched to the specific layer system of the wafer.

Particular challenges arise with wafers containing sensitive layer stacks, such as components with low-k dielectrics in the wiring layers. These porous materials are considerably more mechanically fragile than classic silicon dioxide and are more prone to delamination – the separation of individual layers – during sawing.

After separation, the quality of the cut edges is frequently inspected optically. In addition, the previously generated yield map remains valid: since the dies remain in position thanks to the carrier film, the map can be used to unambiguously determine which of the now-separated dies were already identified as functional during the wafer test, and therefore proceed to the next assembly step, die attach.